Semiconductors.
India's chip bet — a ₹76,000cr Mission (now ISM 2.0), 13 approved projects, its first Made-in-India chip (Micron, Feb'26) and a first fab (Tata-PSMC Dholera) due 2028. World-class at DESIGN (20% of the planet's chip engineers), starting from zero in fabrication.
The thesis in one line: India consumes ~$50bn of chips a year and makes almost none of them — that import bill, plus Taiwan-concentration risk, is the localisation case. India's genuine edge is the front (design — 20% of the world's chip designers) and, increasingly, the back (ATMP/OSAT packaging, now live). The hard, capital-and-know-how core — leading-edge fabrication and equipment/materials — stays Taiwan/US/Netherlands and is a generational gap. Returns are real and near-term in design + ATMP + ESDM; the fab is a subsidised (~50-70% capex), long-dated, yield-binary option, not a base case. The public-market play is ESDM/design proxies until Tata Electronics lists. ISM 2.0's pivot to equipment, materials and design-IP is the smart unlock.
AI, auto/EV, mobile, defence; India consumption ~$50bn → $110bn+ by 2030, ~90-95% imported today — the localisation thesis.
First ATMP live (Micron, Feb'26); first fab Dholera 2028; 13 projects approved — but zero operating fab today.
Fabs $10-20bn; Dholera ₹91,000cr ($11bn), ~70% government-funded. Decade-long, subsidy-dependent payback.
TSMC 72% of foundry; India a late entrant in mature nodes. Design is India's edge; fabrication is the gap.
Running a fab (yield, ultrapure water, power, talent) is unproven in India; subsidy- and foreign-partner-dependent.
Design/ESDM/OSAT = real near-term cash; the fab = subsidised, long-dated bet. Listed proxies re-rated then corrected hard in FY26.
~$800bn (2025) → $1tn+ (2026) — an AI-driven supercycle; AI chips ≈ half of 2026 sales
~$50bn (2025) → ~$115bn by 2030 (~18% CAGR) — but consumption, ~100% imported today
~$18bn committed across 13 ISM/SPECS projects; Tata-PSMC Dholera fab (~$11bn) the anchor
India consumes ~$50bn of chips a year and imports nearly all of them — that import bill, plus Taiwan-concentration risk, IS the localisation thesis. The question is which parts of the chain India can actually serve.
India consumes ~$50bn of chips a year and imports nearly all of them — that import bill (and the strategic exposure behind it) IS the thesis. Auto/EV and AI/compute are the fastest-growing pulls; but localisation realistically starts at the ENDS of the chain — design (front) and ATMP/packaging (back) — on mature nodes, not bleeding-edge AI silicon.
Demand is only useful if India can serve it. Here is each end-market, its localisation horizon, and the honest status — which mostly reads 'designed or assembled here, fabricated abroad'.
The honest state: the value India can localise now sits at the ENDS of the chain — design (front) and assembly/packaging (back) — on MATURE nodes (auto, power, defence). Leading-edge AI/compute silicon — the highest-value, fastest-growing slice — stays imported for years. The localisation story is real but it is back-end-and-design-first, not fab-first.
Semiconductors are a chain, not a product — and India enters at very different strengths along it. This is the single most important map for an allocator: design strong, fabrication absent.
India is strong in the HIGHEST-value slice (design — ~50% of value-added, the fattest profit pool) and rising in the LOWEST (ATMP/OSAT — ~6%, the back-end) — but absent in the capital-and-IP-heavy middle (equipment, materials, leading-edge fab). The strategic catch: India's wins cluster at the design front and the thin-margin back-end, while the durable foundry-plus-tools profit pool stays offshore. Share = approximate industry value-added by stage.
India enters at the ENDS — design (front, a genuine global strength) and ATMP/OSAT (back, fastest-rising) — while the capital-and-know-how core (leading-edge fab + equipment/materials) stays Taiwan/US/Netherlands. ISM 2.0 explicitly pivots to equipment, materials and design-IP to widen beyond fabs — the right move; the leading-edge fabrication gap remains generational.
The question the demand charts can't answer: what is India actually making, and how far behind the frontier is it? Capacity output (fabs, ATMP, first chip) is the localisation proof; the global table is the honest scale check against Taiwan.
The thesis is import-substitution — so the number that matters is how much India will actually make. Per the NITI Aayog roadmap: not much, not soon, and mostly not the high-value chips.
The honest localisation number: India targets just 15-25% self-sufficiency by 2030 — and that share is weighted to mature-node chips + packaging, NOT the AI/compute silicon that dominates the import bill. Dholera is ~70% government-funded; the full roadmap needs $135-180bn with two-thirds from private capital that hasn't arrived. 'Atmanirbhar in chips' is a 2035-2047 project, not a 2030 one.
The honest read: India is building the easier, lower-value ends — design (a real strength) and ATMP/packaging (live and scaling) — plus a first mature-node (28nm) fab by 2028. It has ZERO leading-edge fabrication, ~100% import dependence on AI/compute silicon, and a generational gap to TSMC's 2nm. The investable near-term layer is ESDM/OSAT + design services; leading-edge sovereignty is a 2030s+, heavily subsidy-dependent aspiration.
Tata Electronics (fab + ATMP, unlisted) anchors; Micron leads back-end; the rest is ESDM/design. Shares indicative.
Tata's Dholera fab (~$11bn) dwarfs the rest — but one TSMC year of capex exceeds India's entire mission.
No listed fab pure-play — Tata Electronics is unlisted (IPO the awaited catalyst). Listed exposure is ESDM/design/OSAT proxies (Kaynes, CG Power, Tata Elxsi, Dixon), where semiconductors are a slice, not the whole. True pure-play exposure (TSMC, Nvidia, ASML, Micron) is offshore. Many India names re-rated 200-400% on the ISM theme, then corrected sharply through FY26.
Where the sector actually sits — fab + ATMP are private/strategic; the listed proxies are ESDM. Scale, ownership, and the last marker of value.
India's chip champion; first silicon late'26, full fab 2028 — the sovereign anchor
First commercial Made-in-India chip (DRAM packaging to Dell)
Auto/industrial packaging — listed-parent exposure via CG Power
Listed-company back-end build — the investable OSAT proxy
India's first commercial high-perf SoC — owning the silicon, not just designing it
Indigenous communications silicon — a rare India product-chip company
The fabless design layer — where venture capital enters, and where India's 20%-of-the-world design talent can own the silicon, not just service it.
India's first commercial application SoC — the product-IP white-space
Indigenous processor IP — the open-architecture bet
DLI-backed edge-AI silicon — riding the AI-at-the-edge pull
High-performance compute silicon — ambitious, capital-hungry
Communications silicon — one of India's longest-standing fabless names
Indigenous compute architecture IP
VC read: the capital-light, India-edge layer is FABLESS DESIGN — RISC-V SoCs (Mindgrove, InCore), edge-AI (Netrasemi), HPC (Calligo), 5G/broadcast (Saankhya). DLI funding rose 10× in two years ($5m→$50m), with a target of 50 fabless companies. The genuine white-space is OWNING the chip — product and IP — not just design services: India has the designers but few firms own the silicon. Fabs are not a VC game (capital + subsidy + strategic partner).
A screened, purity-weighted basket of India-LISTED semiconductor exposure — mostly ESDM/design/OSAT proxies (no listed fab pure-play; Tata Electronics' IPO is the catalyst), each weighted by its semiconductor-revenue purity score after liquidity and quality screens.
Real point-to-point anchors: each name rebased to 100 at −3y; the −1y (326) and now (363) levels from its actual 1Y & 3Y returns, purity-weighted. Intra-period linear (daily shape/drawdowns need a price feed).
Rules-based: include an India-listed name if its SEMICONDUCTOR-revenue purity score ≥ 20/100 AND it clears the screens. Weight by purity (exposure-weighted), single-name cap 25%, overflow redistributed pro-rata. Quarterly reconstitution; selection set ex-ante. India-listed basket — no listed fab pure-play yet (Tata Electronics unlisted).
- ✓ Liquidity & size — investable free-float, adequate ADTV
- ✓ Quality — positive profitability (excludes sub-scale loss-makers)
- ✓ Purity — India semiconductor revenue-exposure score ≥ 20 of 100 (filters broad EMS / IT)
Rules-eligible, pending verified data: Tata Electronics (IPO), Syrma SGS, Polymatech, RIR Power, ASM Technologies. Purity = our ESTIMATE of each name's India SEMICONDUCTOR revenue share — most are ESDM/EMS/design-services where chips are a slice, so the basket tracks 'India semi-localisation proxies', not pure fabs (none are listed). Tata Electronics' IPO is the awaited pure-play catalyst. Returns are representative point-to-point figures, not an audited daily-rebalanced backtest.
Selection-bias caution: India semi/ESDM names re-rated 200-400% on the ISM theme, then corrected sharply in FY26 — past returns are upward-biased and NOT a forward estimate. The rules, not the hindsight, are what's intended to repeat.
INFORMATIONAL / RESEARCH ONLY — not investment advice, not a stock recommendation, and not a SEBI Research-Analyst model portfolio. Past performance does not indicate future returns. Figures are representative; precise CAGR/XIRR and a real NAV require audited price series. Do your own research / consult a SEBI-registered adviser.
Chips are dual-use and sovereign — the externalities are strategic autonomy, supply-chain resilience and the water/power a fab demands, not the digital output itself.
Dholera ramps on yield; ATMP scales; fabless winners own product — India a credible mature-node + packaging hub
Micron/OSAT + design services compound; leading-edge stays imported; fab ramps slowly
Dholera yield/ramp issues + subsidy fatigue; India stays a design-plus-assembly economy
Approving fabs is not running them. India has ZERO operating fabrication today; the first (Tata-PSMC Dholera) targets first silicon in late-2026 and full operation in 2028 — and it is 28nm-class, already ~5-6 nodes behind TSMC's 2nm. Fabs are the hardest manufacturing on Earth: yield (the share of working chips) takes years to mature, and a fab needs millions of litres a day of ultrapure water and utterly stable power. The economics close only on heavy subsidy (Dholera is ~70% government-funded) — and there is a deeper trap: a brand-new 28nm fab competes against fully-DEPRECIATED Chinese and Taiwanese 28nm capacity, so mature-node prices may never let it earn its cost of capital without permanent support. The talent gap compounds it — India has 20% of the world's chip DESIGNERS but almost no experienced fab PROCESS engineers, a different and far scarcer skill. If subsidy fatigues or yields disappoint, the leading-edge dream stalls and India stays a design-plus-assembly economy. For an allocator the near-term, investable reality is design + ATMP/OSAT + ESDM cash flows; the fab is a subsidised, long-dated, execution-binary option — not a base case.
Funding is heavily public and subsidy-led — 50-70% capex support (Dholera ~70%) is the deal-maker (and the risk if it fatigues). DLI is scaling the capital-light design layer. A Tata Electronics IPO would open public capital to the fab story; until then the fab layer is private and state-anchored.
Risks quantified, not just listed — the levers that swing the underwriting. Directional, illustrative.
- ↑ Import substitution — India imports ~100% of a ~$50bn (and rising) chip bill; localisation is the structural pull.
- ↑ Geopolitics — Taiwan concentration + US-China decoupling make India a 'China+1' chip destination.
- ↑ Design strength — 20% of the world's chip designers; a genuine front-end advantage.
- ↑ Policy / subsidy — ₹76,000cr ISM + ISM 2.0 + up to 50% capex support + DLI for fabless.
- ↑ AI / auto / defence demand — an AI supercycle globally; auto/EV and defence pull domestically.
- ! Fabrication gap — zero operating fab; leading-edge is a generational, ~$20bn-a-fab barrier.
- ! Subsidy dependence — fab economics rest on ~50% support; policy fatigue is a real risk.
- ! Execution / yield — running a fab (yield, ultrapure water, power, talent) is unproven in India.
- ! Liquidity / exits — no listed fab pure-play; proxies re-rated then corrected hard in FY26.
- ! Global cycle — semis are cyclical; an AI-capex turn or memory glut hits demand and pricing.
ATMP/OSAT and ESDM platforms have real near-term cash flows; fabs are subsidy-and-strategic, not classic PE returns. Back the back-end and design-services scale-ups; treat fab equity as state-anchored.
Fabless design products are the asymmetric layer — RISC-V SoCs, edge-AI, comms silicon — where India has the designers and capital is light. The white-space is owning the chip/IP, not services. Not a fab game.
Listed proxies (Kaynes, CG Power, Tata Elxsi, Dixon) re-rated 200-400% then corrected hard — momentum- and policy-newsflow-driven. Trade the ISM catalysts; respect stretched-then-reset valuations.
Strategic-autonomy + import-substitution + a Taiwan-risk hedge. Sustain the subsidy, but ISM 2.0's pivot to materials, equipment and design-IP is right — don't bet only on fabs; secure water, power and operating talent.
Data vintage June 2026. Anchored to 2025-2026 industry and official prints; figures across sources differ and are reconciled to the cited ranges. Sources: ISM ₹76,000cr, ISM 2.0 ₹8,000cr, 13 projects (India Semiconductor Mission)P · DLI 24 projects, funding 10× ($5m→$50m), 50-firm target (DLI / MeitY)P · Tata-PSMC Dholera ₹91,000cr / first silicon late'26 / fab 2028 (ABHS / Vaishnaw)S · Micron Sanand ATMP live Feb'26, first Made-in-India chip to Dell (press)S · India market ~$50bn→$110bn+; 20% design talent (IMARC / Invest India)S · Listed India semi/ESDM proxies + FY26 returns (Tradebrains / Tickertape)S · Global market ~$800bn→$1tn+, AI ~half, TSMC 72% (WSTS / IDC / Deloitte)S · Tata-ASML MoU; ISM 2.0 equipment/materials pivot (Policy Circle)S · Self-sufficiency 15-25% by 2030, $240bn import risk (NITI Aayog / Business Standard)S · Scorecard scores, value-capture split & basket purity weights — Gravitywell estimateE
Data confidence. Confidence tiers — HARD (official: ISM budget, 13 approved projects, Micron live, Dholera capex/timeline, listed-stock data, policy); FIRM (tier-1: market size ~$50bn→$110bn, 20% design talent, DLI counts, global $ market); SOFT/JUDGEMENT (scorecard scores, purity scores, capex splits, and representative 1Y/3Y returns — hindsight-biased, labelled). Forecasts diverge (India $109-300bn by 2030-35); reconciled to cited ranges.
Sourcing. Every figure is sourced and dated. We tier provenance — Primary (official, regulatory, exchange or company filings), Secondary (tier-1 industry research and reputable media), and GW estimate (our own reconstruction or opinion, labelled, never presented as external fact). We prefer primary where it exists, reconcile divergent prints to cited ranges, and hold every number point-in-time — dated, and never silently restated; revisions publish as dated changes.
Fact vs opinion. Facts vs opinion — market sizes, official prints, prices, named deals and agency ratings are sourced facts (Primary/Secondary). Scores, grades, purity weights, scenario paths and indicative sparkline points are Gravitywell's analytical opinion (GW estimate) — labelled, not presented as external data.
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